The present disclosure relates generally to magnetic random access memory (MRAM) devices and, more specifically, to an MRAM device having a low-k dielectric material.
MRAM devices often include an inter-metal dielectric (IMD) layer interposing an MTJ cell or stack and a bit line, word line, program line, or other conductive layer. However, the electrical characteristics of the material employed in the IMD layer can detrimentally affect performance of such MRAM devices. For example, high permittivity of the IMD layer can increase RC delay of the MRAM devices during read/write operations. Undesirable electrical characteristics of the IMD layers can also undesirably cause fault signal detection during multiple-byte read operations.
One attempt at solving such problems has been to increase the thickness of the IMD layer, at least in the region interposing the MTJ stack and a proximate bit line, program line, and/or word line. However, such an increase expands the overall size of the MRAM device and, consequently, the chip and end-use apparatus incorporating such MRAM devices. Moreover, those skilled in the art will recognize that an increase in physical size of MRAM devices and circuit, chips, etc. incorporating the devices will be accompanied by a corresponding increase in cost per chip. Furthermore, chip reliability is often inversely proportional to chip size, such that MRAM devices incorporating thicker IMD layers can exhibit excessive failure rates.
Accordingly, what is needed in the art is a memory device that addresses the above discussed issues, a method of manufacture thereof, and a system including the same.